The processing architecture
SAP 7100X uses a Cortex-M0 control processor alongside dedicated Matrix, FIR, Delay, Gain and Router blocks. The functional diagram describes their responsibilities; it is not a physical silicon floorplan.
Physical input and output
The preliminary datasheet lists up to 64 TDM input channels and 64 TDM output channels. External audio conversion and power amplification must be considered separately when building a complete system.
FIR configurations
The FIR engine has 32 computation cores. Its resources can be allocated to different channel/tap combinations; these are processing configurations, not separate claims of physical interface capacity.
- 128 channels × 1024 taps
- 64 channels × 2048 taps
- 32 channels × 4096 taps
Configuration and audio paths
Control firmware supplies routing and coefficient settings; dedicated hardware performs the audio processing. Keeping these paths separate makes a system diagram easier to read and avoids depicting configuration data as an audio stream.
Planning an integration
- Confirm the input/output interface and required channel count.
- Select FIR resources for the intended filter lengths.
- Plan external conversion, amplification and system control.
- Verify timing and behavior using the applicable silicon and documentation revision.
Reference and scope
Reference: SAP7100X Datasheet V1.2, marked Preliminary, reviewed on 11 October 2026. The cover and revision-history dates differ; confirm the applicable revision with SineMedia before integration.
Reference sections: control and functional architecture, pages 9 and 28; FIR resources, page 27. No NPU, ADC/DAC or power-amplifier capability is inferred here.
